The present invention relates to improving the electrostatic discharge (ESD) protection of semiconductor components and structures of integrated circuits.
ESD protection is an important consideration in integrated circuit design, particularly, as semiconductor structure and component dimensions are scaled down to deep submicron (i.e., less than 0.65 xcexcm) resolutions. During an ESD event, charge is transferred at a high voltage to a pin of an integrated circuit chip during a short duration, i.e., typically less than 1 xcexcsec. Most semiconductor integrated circuits include MOS devices such as MOSFETs with very thin gate oxides or lightly doped drains and sources which are highly susceptible to damage during ESD events. As such devices are made smaller, they can be damaged by even lower voltage ESD events.
FIG. 1 depicts a schematic of an ESD protection circuit 10 of an integrated circuit. Circuits 16 and 18 provide ESD protection to input buffer 12 from ESD voltages which may be applied to the input pad 14. When an ESD event occurs, the diodes of the circuit 16 shunt most of the ESD charge. When the polarity of the ESD voltage is negative, diode D1 shunts ESD charge to the VSS bus and when the polarity of the ESD voltage is positive, diode D2 shunts ESD charge to the VDD bus. The circuit 18 includes a resistor R connected in series with a grounded FET clamp M0. The circuit 18 limits the voltage which is applied across the gates of the input buffer 12. The core clamp 20 provides ESD protection to the VDD and VSS power busses by transferring ESD charge between the VDD and VSS power busses during an ESD event.
Most ESD protection devices are designed to be triggered when a high ESD voltage is applied between two pins of an integrated circuit chip. However, recent attention has been directed to protecting against ESD voltages which may be applied across power busses of the integrated circuit chip. See C. Duvvury, R. Rountree and O. Adams, Internal Chip ESD Protection Beyond the Protection Circuit, I.E.E.E TRANS. OF ELEC. DEVS., vol. 35, no. 12, p. 2133-38, December, 1988; J. LeBlanc and M. Chaine, Proximity Effects of xe2x80x9cunusedxe2x80x9d Output Buffers on ESD Performance, I.E.E.E. IRPS PROC., p. 327-30 (1991). These references note that the ESD protection circuits provided between the VDD and VSS pins may not provide sufficient protection to the internal devices of the chip. Rather, the chip may, by virtue of the layout of the regions and structures of the internal devices, incorporate parasitic bipolar junction devices which turn-on in advance of the triggering of the ESD protection circuits resulting in damage to the internal devices.
Consider, for example, the circuits depicted in FIGS. 2-4. FIG. 2 depicts the schematic of two closely placed internal circuits. In particular, a first circuit 22 includes an NMOS transistor N1 which is placed laterally adjacent to an NMOS transistor N2 of a second circuit 24. An overhead view of this configuration is shown in FIG. 3 and a cross-section of this configuration, taken at the line X-Xxe2x80x2, is shown in FIG. 4. The transistor N1 has a gate 30, a source 36 and a drain 38. The source 36 and drain 38 are N+ regions which extend from the surface of a substrate 34. The transistor N2 has a gate 30xe2x80x2, a source 40 and a drain 42. Like the transistor N1, the source 40 and drain 42 are N+ regions which extend from the surface of the substrate 34. The drain 38 of transistor N1 is connected to the VDD power bus line 32 by contacts 28 the source 40 of the transistor N2 is connected to the VSS power bus line 32xe2x80x2 by contacts 28xe2x80x2.
As shown in FIG. 4, the drain 38 is adjacent, and in close proximity, to the source 40. The N+ drain region 38, N+ source region 40 and P-conductivity type bulk substrate 34 between the source 40 and drain 38 form an NPN parasitic bipolar junction device 44. During an ESD event, an ESD voltage may be applied between the VDD power bus line 32 and the VSS power bus line 32xe2x80x2. Because of the proximity of the N+ drain 38 and source 40 region, the requisite turn-on voltage of the parasitic BJT (bipolar junction transistor) 44 can be as low as 13 volts. The ESD voltage between the VDD and VSS power bus lines 32 and 32xe2x80x2 may be sufficiently high to turn on the parasitic BJT 44 and cause it to operate in xe2x80x9csnap-backxe2x80x9d mode. This can result in the flow of a large current which can damage the components and structures of the integrated circuit. Note the BJT 44 can turn on at a lower voltage than the circuit which provides ESD protection for ESD events that occur on the power busses (e.g., the core clamp circuit 20 of FIG. 1) and thereby cause damage during an ESD event despite the provision of such ESD protection circuitry.
The prior art has suggested to avoid such internal damage owing to parasitic bipolar junction devices by increasing the spacing between various components and structures (e.g., between the drain 38 and the source 40 of the transistors N1 and N2) by 20 xcexcm. However, this wastes a large amount of precious space on the integrated circuit chip thereby reducing the density of structures and components on each integrated circuit chip. Furthermore, this does not completely prevent the parasitic bipolar junction device from damaging the integrated circuit.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.
This and other objects are achieved by the present invention. According to one embodiment, an ESD protected structure is provided with a heavily doped polycrystalline silicon region of a first conductivity type. The heavily doped polycrystalline silicon region is disposed on a substrate surface and is connected to a power supply voltage. A lightly doped region, of the first conductivity type, is disposed below the substrate surface and below the polycrystalline silicon region. A first heavily doped region, of the first conductivity type, of a first MOS device is disposed below the substrate surface, and contained entirely within the lightly doped region. A second heavily doped region, of the first conductivity type, of a second MOS device, is disposed below the substrate surface, and separated from the first region by a portion of the lightly doped region and a second conductivity type doped portion of the substrate.
Illustratively, the separation of the first and second regions by a portion of the lightly doped region increases a turn-on voltage of a bipolar junction device that includes the first and second regions, the portion of the lightly doped region and the second conductivity type doped portion of the substrate. (The bipolar junction device illustratively is a parasitic BJT in which the first region and lightly doped region form the collector, the second conductivity type portion of the substrate forms the base, and the second region forms the emitter of the parasitic BJT.) The increase in turn on voltage, in turn, tends to prevent the bipolar junction device from turning on, during an ESD event, before an ESD protection device that protects the structure from ESD events which occur within the power supply voltage.
According to another embodiment, the ESD protected structure is fabricated as follows. The heavily doped polycrystalline silicon region, of a first conductivity type, is formed on a substrate surface. Impurities are illustratively thermally diffused from the polycrystalline silicon region below the surface to form the lightly doped region of the first conductivity type. The first heavily doped region of the first conductivity type of the first MOS device is formed below the substrate surface, and entirely within the lightly doped region. The second heavily doped region of the first conductivity type of the second MOS device is formed below the substrate surface at a particular location such that the first and second heavily doped regions are separated by a portion of the lightly doped region and a second conductivity type portion of the substrate.
In short, an ESD protected structure, and method of its fabrication, are provided. The ESD protected structure is easy to form using MOS fabrication compatible processes and reduces damage to internal circuits from ESD events which occur on the power busses.